Digital counter employing logic gating network independent of counter stage (s) control to effect reset operation



June 25. 1968 J. D. NEWMAN ET AL 3,390,340 DIGITAL COUNTER EMPLOYINGLOGIC GATING NETWORK INDEPENDENT OF COUNTER STAGEKS) CONTROL TO EFFECTRESET OFERATION 8 'Sheets-Sheet 1 Filed Aug. 28, 1963 IDNEWMAN 8 a AELLlOT ATTORNEY ET AL June 25. 1968 3,390,340 ETWORK J. D. NEWMANDIGITAL COUNTER BMPLOYING LOGIC GATING N INDEPENDENT OF COUNTER STAGE(S)CONTROL TO EFFECT RESET OPERATION 8 Sheets-Sheet 5 Filed Aug. 28, 1965IDNEWMAN & R A ELLtOT Wyfn'raes BY Uwiaw f. P. M

ATTORNEY June 25. 1968 J. D. NEWMAN ET AL 3,390,340

DIGITAL COUNTER EMPLOYING LOGIC GATING NETWORK INDEPENDENT OF COUNTERSTAGE(S) CONTROL TO EFFECT RESET OPERATION Filed Aug. 28, 1963 8Sheets-Sheet 4 A B Q 60 67 62 63 0 7 0 7 0 l 0 7 65 66 67 68 69 70 77 72ej G GB (ci)- lNPUT "64 6 FIG.4.

PR IOR AR T B C D A B C D O 0 O 6 O O 2 O` 7 O O 3 O 8 O l O 4 l O 9 0 OO 5 I O O O O O ID.NEWMAN & R. A. ELLlOT v Mymmes sy MMM 5.2 5%

ATTORNE Y June 25, 1968 1. D. NEWMAN ET AL 3,390,340

DIGITAL COUNTER EMFLOYING LOGIC GATING NETWORK INDEPENDENT OF COUNTERSTAGE(S) CONTROL TO EFFECT RESET OFERATION Filed Aug. 28, 1965 8Sheets-Sheet 5 RECOGN/SE O X FIG.6. Y Z ou'rpur o/v/s/ov NUMBER RESET95557 CONTROL vpurs PAT/0 A B c 0 w X y z /o o o o o o o o o o o o o o oo 2 9 o o o o o o J a o o o o 4 7 o o o o 5 6 o o o o 6 5 o o o o o o 74 o o o o e 3 o o O CLOSES GATE 78 l OPENS GATE 78 IDNEWMAN s R.A.ELLIOTMyymes BY Willow, 5.?

ATTORNEY June 25, 1968 J. D. NEWMAN ET AL lTAL COUNTER EMPLOYING LOGICGAT TO EFFECT RESET OFERATION 8 Sheets-Sheet 6 Filed Aug. 28, 1963 ID.NEM/MAN 5 RA. ELLIOT MMM 7025 sy Maw' 5 2 5% ATTORNEY June 25, 1968 J.D. NEWMAN ET AL 3,390,340

DIGITAL COUNTER EMPLOYING LOGIC GATING NETWORK INDEFENDENT OF COUNTERSTAGE(S) CONTROL TO EFFECT RESET OPERATION Filed Aug. 28, 1963 8Sheets-Sheet 7 B/S TA BLE BISTA BLE TRIG GE R FROM SUCCEED/NG STAGE B/STA BLE RESET RECOGN/T/ONR B/STABLE SET 4:/

RESET B/NSTABLE SET =O IDNEWMAN K.A.ELLIOT ATTORNEY United States PatentO 3,3%,340 DIGITAL COUNTER EMPLOYING LOGIC GAT- ING NETWORK INDEPENDENTOF COUNTER STAGE(S) CONTROL TO EFFECT RESET OPERATION John D. Newman,Hayling Island, and Robert A. Elliot, Petersfield, England, assignors toPlessey-U.K. Limited, a British company Filed Aug. 28, 1963, Ser. No.305,232 Claims priority, application Great Britain, Aug. 31, 1962,33,600/ 62 7 Claims. (Cl. 2328-48) This invention relates to digitalcounters.

In certain applications of digital counters it is desirable for thecounter to sum a train of events up to a predetermined number and thenboth to deliver a significant Output and to commence a new countingcycle with the next input event. This can demand -very high operatingspeeds, not only in the counter stages themselves but also in theancilliary circuits for recognising the desired total and for resettingthe counter. An application of particular importance occurs in frequencygenerators in which a high-speed digital counter is used as a frequencydivider of arbitrary scale, producing any desired submultiple of aninput frequency.

The maximum frequency of operation of a counter used as a frequencydivider in this way is limited partly by component operating speeds andpartly by the time taken to recognise the fact that the counter hasreached a predetermined total and subsequently to reset the counter to asecond predetermined figure, which may or may not be zero. In a counteremploying serially-arranged counter stages, With carry pulsestransmitted between stages, recognition speeds are limited by cumulativedelays between *stages and the resetting operation may be complicated bythe generation of unwanted carry pulses.

According to the invention, a digital counter includes at least twomulti-stable devices having inputs arranged to receive input ulses froma common input line through gating devices which determine the effect ofan input pulse on the respective bistable devices and which are arrangedto be set each in correspondence with the state of at least one of thebistable devices in such a way that a succession of input pulses causesthe counter to progress through a repeated series of counting states,the counter including also means for recognising when the counter hasarrived at a selected one of its possible states and for :responding tothis recognition in such a way that the next consecutive input pulse isemployed as a resetting pulse for resetting the counter to recommencecounting from a selected one of its possible states.

In such an arrangement no question of cumulative stage delays arises,the time taken to recognize any number being determined by the timerequired to set an individual counting stage. The resetting of thecounter between two consecutive input pulses is no longer necessary,avoiding the use of ancillary circuits such as reset pulse generatorshaving high operation speeds.

A further aspect of the invention consists in an electrical oscillationgenerator including a Variable-frequency oscillator, a variable-ratiodivider consisting of a digital counter according to the presentinvention, as hereinbefore defined, arranged to count the cycles of theOutput waveform of the Variable-frequency oscillator and to deliver anOutput pulse each time a predetermined number of cycles is counted, andmeans for controlling the frequency of the oscillator so as to reduce tozero the deviations of the repetition frequency of the divider outputpulse train from a fixed master frequency.

The foregoing and other features of the invention will 3,3%,340 PatentedJune 25, 1968 ice:

be evident in the following description of various preferred embodimentsthereof.

The description refers to the accompanying drawings, in which:

FIGURE 1 is a general block diagram of a Variablefrequency oscillationgenerator.

FIGURE 2 is a more detailed block diagram of the coarsefrequency-control circuits of the generator,

FIGURE 3 is a block diagram of the fine frequency control circuits ofthe generator,

FIGURE 4 shows schematically a decade counter arrangement,

FIGURE 5 shows the counter sequence for the arrangement of FIGURE 4,

FIGURE 6 shows a modified form of decade counter suitable for use in thegenerator shown in FIGURES 1-3,

FIGURE 7 is a resetting code chart for FIGURE 6,

FIGURE 8 shows a block diagram of a multi-stage counter employing thedecade counter of FIGURE 6,

FIGURE 9, is a more detailed diagram of a single decade of the counter,and

FIGURES 10 and 11 show two alternative counter arrangements.

The circuit elements shown in block form in the drawings are allexamples of devices in widespread current use, so that detaileddescription of their circuit arrangements is unnecessary.

The apparatus shown in the drawings forms an oscillation generatorcapable of covering a wide 'frequency range, in fixed frequency steps,with accuracy determined by a single frequency source, such as acrystal-controlled oscillator, that constitutes its internal standard offrequency. Any frequency within its range can be set up directly bymeans, for example, of a series of decade switches calibrated directlyin frequency.

Referring now first to FIGURE 1, the oscillator generator comprises acrystal-controlled master oscillator 1 serving as a frequency standardand operating at a frequency F and a digital frequency divider 2operating at a fixed division factor K to produce on its Output line 3,a train of pulses at a repetition frequency F /K. The useful outputs ofthe generator is obtained from a slave oscillator 4 tunable over therequired frequency range. In order to control the frequency of the slaveoscillator 4 to a selected integer multiple of the base frequency F /K,the Output of the 'slave oscillator 4, in addition to being supplied toan Output line 5, is also supplied to a second frequency divider 6,which likewise operates on the digital principle, but the divisionfactor N of which, in contrast to that of divider 2, is adjustable toany one of the digital numbers corresponding to the multiples of thebase frequency at which slave oscillator 5 is required to be operable.Both dividers 2 and 6 are arranged to 'supply a pulse Output, and boththe Output of fixed-ratio divider 2, via its Output line 3, and theOutput of variable-ratio frequency divider 6, via a line 7, are suppliedas inputs to a frequency comparator and controller 8 which, via acontrol loop 9, varies the tuning of the slave oscillator 4 to increaseor decrease its oscillation frequency when the number of pulses receivedfrom line 3 exceeds the number of pulses received from line 7 or viceversa. When the frequency of pulses produced by the slave oscillator isclose to the desired frequency, comparatively long periods will arise inwhich no excess pulse is received from either lines 3 or line 7, andaccordingly a phase-responsive fine control is arranged to be providedin these Circumstances by means of a phase comparator 10 which producesan Output proportional to the phase difference between the pulsesreceived respectively from lines 3 and 7, the phase-comparator Outputbeing utilised for a fine control of the slave-oscillator frequency,firmly locking that frequency to the selected multiple of the basefrequency produced from the frequency standard.

One form of the frequency comparator and controller 8 of FIGURE 1 isshown in more detail in FIGURE 2. The two respective outputs of thefixed-ratio frequency divider 2 and the variable-ratio frequency divider6 are fed by their associated output lines 3 and 7 to -two identicaldelay networks 11 and 12 which each have two outputs 1151, 11b and 12a,121) respectively. The output bearing the index a differs from the inputby the fact that each pulse is widened, so that each pulse extends overa greater portion of the pulse cycle than the input pulse, while thepulses supplied through the line 'bearing the index b are delayed intime compared with the input pulses. The delayed output pulses on lines1117 and 12b are fed to a binary or bistable device 13 which is soarranged that a pulse from line 11b will put the device 13 into one ofits stable states, thereby opening a first gate 14 and closing a secondgate 15 while an input via line 12b will put the bistable device 13 toits other stable position, in which it closes gate 14 and opens gate 15.Assuming that the base frequency F K is equal to the frequency F /N ofthe pulses in line 12b (F being the frequency of the slave oscillatorselected by adjusting the Variableratio frequency divider 6 to the ratioN) pulses will arrive alternately on lines 11b and 12b, each pulsefinding the gate 14 or in its own path closed and causing it to beopened and the other one closed by changing over the 'binary 13. As aresult neither gate 14 nor gate 15 will pass any pulses. If on the otherhand the frequency of the slave oscillator is, for example, somewhatlower than the selected frequency F the spacing of the pulses from line1217 is longer than that of the pulses from line 11b, so that, at leastoccasionally, a pulse from line 12b will be followed by two successivepulses from line 11b before the next pulse arrives from line 12b. Whenthis occurs, the first of these two successive pulses will change overthe binary 13 to open gate 14 and close gate 15, as before; but thesecond of the two pulses will find gate 14 already open and willtherefore pass through gate 14 and by a common line 16 to a binarycounter 17, each step of which varies by one unit 'the reactance of aswitched reactor set 18 forming part of the tuning circuit of the slaveoscillator.

The binary counter 17 is of the reversible type; the binary device 13 isarranged when set to state O by a pulse from the master oscillator vialine 11b to energise a forward control line 17b of the counter 17, andconversely when set to state 1 'by a pulse from the slave oscillator vialine 12!) to energise a reverse control line 17a. The counter is thusconditioned for forward or reverse counting when subsequently receivingany gated pulse via line 16, making the appropriate positive or negativecorrection to the tuning of the oscillator 4.

Sprious pulses may appear in line 16 when `a -pulse from one inputappears so shortly after a pulse from the other input that the gates 14and 15 have not yet had time to adopt their appropriate states. Toprevent such spurious pulses from reaching the counter a coincidencedetector 19 is provided, having two inputs from the widened pulseout putlines 11a and 12a. If two pulses from delay circuits 11 and 12 followeach other in very close succession, the widened pulses will overlap.The detector 19 recognises this overlap and produces `an output in aline 20 leading to an inhibit gate 21 at the input of the binary counter17; since the pulses applied to line 16 are delayed, the inhibit gate 21will be reliably closed when there is any chance of sprious countingpulses arriving in line 16.

It will be understood that the counter 17 may be utilised in variousways to control the frequency of the slave oscillator 4. In particularit is possible to arrange an electromechanical coarse tuning system inwhich a motordrivcn Variable capacitor, with or without. associatedrange sclcction switches, is controlled by n scrvo-mcclp anism arrangedto set the capacitor shaft to the angular position represented by thestate of the counter 17, a binary-coded disc of known type being used asa positional :pick-off. This arrangement would be advantageous if theoscillation generator was incorporated, for example, in a radiotransmitter having tuned amplifier stages: the provision of a mechanicaloutput corresponding to the coarse tuning of the primary oscillationgenerator would enable all the tuned circuits of the transmitter to beset for operation at a required frequency by a single operation.

FIGURE 3 of the drawings shows the phase control arrangements for thefine frequency control of the slave oscillator 4. The main phase-controlloop consists of the phase comparator 10, in which the relative phase ofthe pulse trains derived from the slave oscillator 4 through theVariable divider 6, and from the frequency standard source 1 (FIGURE l)and the fixed divider 2, is determined, the output from the phasecomparator 10 acting to control the frequency of oscillation of theslave oscillator 4 through a Variable reactance device 50.

The phase comparator 10 includes a saw-tooth generator 51 triggered bythe incoming pulse train from the frequency standard source 1, producinga rising or falling saw-tooth waveform whose repetition frequency isequal to Fa/K.

A sampling and storage circuit 52 samples the sawtooth output of thegenerator 51 at instants determined by the arrival of each pulse fromthe Variable divider 6. The sampled saw-tooth level is held in the store52 between sampling instants. If the two pulse trains have exactly thesame repetition frequency, their phase relationship remains constant, sothat the saw-tooth output of generator 51 is sampled at the same time ineach cycle and the output 53 .of the comparator 10 is a uni-directionalvoltage of constant level. If the two pulse trains differ slightly infrequency, the comparator output 53 will be a sawtooth waveform ofstaircase profile, whose repetition frequency is proportional to thedifference between the frequencies of the two pulse trains. This signalis applied to the Variable reactance device 50, which acts upon theslave oscillator 4 so as to vary its output frequency in the correctsense for reducing the phase error detected by the comparator 10, thusclosing the phase loop.

If the storage device 52 is of a simple nature, such as a capacitorcharged to the storage level at each sampling instant, there is the riskthat a change in the stored level during the sampling interval willresult in the output 53 of the store having components of the frequencyof the pulse trains applied to the comparator 10. These components couldreset on the slave oscillator 4 through the Variable reactance control50 to produce frequency modulation of the slave oscillator output. Toprevent this a lowpass filter 54 is included in the phase control loopbetween the store 52 and the reactance device 50. The filter 54 has onlyto ensure that components of the name order as the pulse repetitionfrequencies are adequately attenuated before the output signal 53 of thestore 52 is applied to the Variable reactance device 56, and may be asimple CR filter or passive integrator. Its presence in the phasecontrol loop will effectively inhibit the loop from responding to therelatively large difference frequencies between the two pulse trainsthat are properly to be dealt with by the frequency control loop shownin FIGURE 2. However the presence of the filter means that the responseof the phase control loop to relatively large phase differences betweenthe two pulse trains, such as may exist immediately after locking of onefrequency control loop, will also be restricted. An inhibit gate 55 istherefore provided which by-passes the filter 54 during the periodimmediately following frequency locking in which the phase control loopis searching for phase lock. The gate 55 is opened, bypassng the filter54, when the frequency loop presence detector 56, cnergisctl from thercvc'siblc binary counter 17 in FIGURE 2, shows that frequency lockinghas hccn achieved as shown by the counter remaining in the same statefor an appreciable period; and is closed again when the phase lockdetector 57, energised from the binary gate 13 in FIGURE 2, shows thatphase lock has been achieved, as shown by the mark/space ratio of thesignal in line 17a or 17b remaining constant.

The slave oscillator 4 is provided with an automatic gain control loop,indicated diagrammatically at 58, for stabilising the amplitude of itsoutput waveform. The automatic gain control loop is closed through agate 59 actuated from the phase lock detector 57. The gate 59 is closed,preventing the operation of the automatic gain control, until phaselocking occurs. Thus, the slave oscillator automatic gain control loopis inoperative during tuning of the oscillator, and only comes intooperation after the correct operating frequency has been set up. Underthese conditions the automatic gain control loop can have a higher gainand a longer time constant, thus permitting a more consistent amplitudecontrol and lower harmonie content of the output.

The lockingin sequence occurring when the slave oscillator 4 is to beset to a given frequency is as follows. The frequency-responsive coarsecontrol loop first tunes the slave oscillator to approximately therequired frequency -while the phase-sensitive fine control and the slaveoscillator automatic gain control loops are suppressed. The frequencysensitivity of the coarse control loop depends largely on thearrangenents adopted for varying the slave oscillator frequency underits control. With the arrangement shown in FIGURE 2, in which the coarsecontrol loop is arranged to switch inductors or capacitors to pull theslave oscillator towards the required frequency, setting to perhaps 1%of the desired frequency may be achieved by this means.

After frequency locking has been achieved, the phase control loop takesover control of the slave oscillator 4, its filter 54 being by-passed soas not to interfere with its operation. The frequency control loop andthe slave oscillator automatic gain control loop are inoperative.Finally phase locking occurs, the low-pass filter 54 is introduced intothe phase control loop and the slave oscillator automatic gain controlloop is closed. The oscillation generator is now set up for deliveringthe required output frequency.

The function of the Variable frequency divider 6 will now be consideredat greater length, since the operation of the frequency generator isvery largely limited by the maximum speed at which this counter canreliably perform its function. The divider 6 is a variable-ratio scaleror counter circuit, counting input pulses corresponding to cycles of theslave oscillator frequency and delivering an output pulse each time thecount reaches a preset value. It must therefore be capable of countingat speeds up to the maximum operating frequency of the slave oscillator,of giving substantially instantaneous recognition when the preset totalis reached and of resetting to begin a new counting cycle before thearrival of the next consecutive input pulse. Counter arrangements forachieving these functions will now be described.

FIGURE 4 shows the basic arrangement of a single decade counterincluding four bistable devices or counting stages 60, 61, 62, 63, whichare fed with an input pulse train from a common input line 64 throughAND gates 65 to 72. The setting of these gates 65 to 72 determine towhich of the four bistable devices 60 to 63 a given input pulse isapplied, and also determines whether the pulse is applied to the set 0or set 1 input of each bistable device. The gates are themselvescontrolled by the states of the bistable devices, each gate beingconnected to an output or a combination of outputs of the bistabledevices. These combinations are so arranged that a train of tenconsecutive input pulses applied to the input line 64 will cause thecounter to cycle through the ten successive states, representing thedigits O to 9, shown in FIGURE 5.

The decade counter shown in FIGURE 6 is arranged to operate as afrequency divider, producing an output pulse train whose repetitionfrequency is the frequency of the input pulse train divided by anyfactor between 1 and 10. The decade may of course form a unit of amultidecade divider. To perform this function the counter is arranged torecognise the occurrence of state 0 (0000 in the counter code) andthereupon to deliver both a significant output on output line 73 and agating pulse on line 74. The gating pulse, which appears immediately inthe state to be recognised is set up on the bistable devices 60 to 63,closes an inhibit gate 75 and opens a further gate 76, thus divertingthe next input pulse to arrive to a line 77 from which gates 78 connectwith the inputs to the bistable devices. The operation of the gates 78is controlled by four external inputs W, X, Y and Z, whose state isdetermined by external switching in accordance with the number it idesired to reset in the stage.

Thus immediately the recognition state is achieved, the next input pulseto arrive is blocked from the normal counter input and re-routed to actas a resetting pulse through gates 78: on resetting the recognitionstate vanishes, gates 75 and 76 revert to normal and counting continueswith the next input pulse.

FIGURE 7 of the drawings shows the division code, that is to say therelationship between the division ratio to be established by the stage,the number reset in the stage, and the control inputs necessary toachieve this.

It will be seen that resetting of the stage is achieved by a pulse ofthe input train, the insertion of a reset pulse between two consecutiveinput pulses being avoided. It will also be noted that the state to berecognized by the counter, i.e. state 0, is achieved immediately thelast pulse of the train acts upon the appropriate bistable device 10 to13; there are no inter-stage connections within the decade to result incumulative delay effects. The resetting operation is performedsimultaneously on each bistable device, and there are no inter-devicecarry pulses to complicate the resetting process.

FIGURE 8 of the drawings shows the first two decades of a counter havingthree or more decade stages. Each decade is generally similar to thatshown in FIGURE 6 but the presence of the adjacent stages necessitatesslight detailed modifications in the means adopted for the routing andcontrol of the input pulses for resetting purposes. (The two counterstages 80 and 81 are assumed to be decade stages for simplicity but ingeneral may have any radix M and N respectively). Each stage includes anadditional bistable 82 and 83 respectively which is triggered by therecognition state of the next following stage of the counter. Thisbistable performs three functions; (a) it allows the faster stage toattain its recognition state; (b) it isolates the slower stage which canthen be reset without waiting for the ultimate recognition state; and(c) it destroys the recognition state in the first pulse afterrecognition, even if the condition of first counter stage does notchange. Function (c) allows the counter as a whole to divide by factorssuch as 11, 21, 31, although a single decade could not in itself divideby 1.

Consider the operation of the second stage 81. Its bistable 83 is set toB=0 and therefore the input control gate 84 (corresponding to gate 75 ofFIGURE 6) allows carry pulses from stage 80 to pass to the input ofstage 81. Carry pulses from stage 81 pass to a subsequent stage, notshown. When this subsequent stage reaches its recognition state theshort pulse resulting from the differentiation at 85 of the pulse on itsrecognition line 86 is used to switch the bistable 83. Counter stage 81continues to count its input pulses until it reaches its recognitionstate R M-l. The signal on its recognition line 87 closes the inputcontrol gate 84, opens the reset gate 88 and triggers the bistable 82 ofthe first stage. The next carry pulse from the first stage is blockedfrom the counter input and passes through the reset gate 88 to the stagereset line 89, resetting the stage to the state determined by the resetcontrol inputs W X Y Z The same pulse resets bistable 83 to B O,breaking the recognition state by opening gate 90 and re-opening gate 84to allow counting to recommence. The first stage 30 now proceeds in thesame way to its own recognition state, which when reached fulfills themultiple recognition condition for the counter as a whole and providesan Output pulse on line 91.

The counter as a whole may include any number of stages, all except thelast stage being identical with those shown in FIGURE 8. The recognitionpulse of the last stage is applied without gating to the bistable (suchas 83) of the preceding stage and may also be employed to reset the laststage.

Between the two stages 80 and 81 of radix N and M respectively shown inFIGURE 8 a carry pulse will be transmitted for the state N of the firststage. Since (N -1) is the recognition state there will always be atleast N pulses between each pair of successive carry pulses, even whenresetting occurs. Thus the counting speed of the second stage can safelybe smaller than that of the preceding stage by a factor N.

FIGURE 9 shows a diagram of single decade stage corresponding to one ofthe two stages 80 and 81 shown in FIGURE 8. The counter itself consistsof four bistables 95 arranged for parallel-fed counting as describedwith reference to FIGURES 4, and 6, although the code employed is notthe same. Gates 96 are sequencing gates corresponding to gates 65-72 inFIGURES 4 and 6; gates 97 receive the reset control inputs W, X, Y, Z;bistable 98 and its associated gates perform the function of thebistables 82 and 83 (FIGURE 8) and gates 84, 88, 90, etc. The figureemploys Conventional logical rotation and is self-explanatory; itsoperation will not be described in the text.

FIGURE of the drawings shows an alternative form of counter/ divider, inwhich an alternative solution to the problem of a rapid resetting of thecounter is proposed. The main counter 100 shown in this figure consistsof three decade counters 101, 102 and 103, each of Which may be aparallel-fed decade of the kind shown in FIG- URE 4.

The main counter 100' has associated with it an auxiliary counter 104,which is a simple counter counting from 0 to 9. Recognition pulses fromthe main and auxiliary counters are used to trigger main and auxiliarypulse generators -105 and 106 respectively and also to change over abistable trigger device 107 the Output of which controls AND gates 108and 109.

The divider functions in the same manner as that previously described byrecognition of a first given figure and subsequent resetting to a secondgiven figure, the difference between the two figures giving the divisionratio. From the point of view of describing the resetting arrangementsof FIGURE 10 it is immaterial whether or not either of these two figuresis zero. The sequence of Operations for the arrangement of FIGURE 10 isas follows.

Assume that gate 108 is open so that counting is proceeding in the threedecades of the main counter 100. When the counter reaches thepredetermined recognition number set into it, it delivers an Output onits recognition line 110. This output has a three-fold effect. Itdelivers a significant Output to an Output line 111, it sets thebistable device 107 to its "0" state, and it triggers the main resetpulse generator 105. The reset pulse generator applies the resettingpulse to decades 102 and 103 of the nain counter, but not to thehigh-speed decade 101, for reasons that will presently appear. Theswitching of the bistable device 107 closes gate 108 and opens gate 109,thus preventing the next consecutive input pulse arriving at the input112 from reaching the main counter 100 and applying it to the auxiliarycounter 104. Counting then proceeds in the uxiliary counter 104 untilrecognition occurs of some preset figure. The recognition Output on line113 resets the bistable device 107 to state 1 transferring the inputpulse train back to the main counter 100, and triggers the auxiliaryreset pulse generator 106 to reset the auXiliary counter 104. Thecounting sequence then recommences with counting in the main counter100.

It will be seen that with this arrangement the auxiliary counter 104 isemployed to add any number between 0 and 9 to the number preset on themain counter 100, of which the least significant digit will always bezero. The division ratio is thus the sum of the two figures set in themain and auxiliary counters.

Resetting of either counter section is carried out while counting isproceeding in the other section and is therefore not limited in time tothe period between consecutive input pulses.

In this arrangement the high-speed decade 101 of the main counter doesnot need to be reset upon each total recognition by the main counter,since it merely remains at 0. This simplifies the design of the counter.Although this is to some extent offset by the provision of the auxiliarycounter 104, this counter need only be a simple device and does notover-complicate the system: it has to count through a single decade(0-9) but it need not be a true decade stage, since it does not have togenerate a carry pulse for a subsequent decade.

FIGURE 11 of the drawings shows schematically a third form of divider.The counter proper consists of three counting decades 160, 161 and 162;decades 161 and 162 are Conventional, but the high-speed decade isreversible. Count recognition is eifected by the usual preselectedoutputs 163 and 164 for the two lower speed decades and by twoalternative recognition outputs 165 and 166 for the high-speed decade.The operation of the circuit is as follows.

Assume that the counter is counting normally until the presetrecognition number occurs. A forward recognition pulse is delivered online 167 to open gate 168. The next consecutive input pulse in the trainpasses through gate 168 to switch a bistable device 169, andsimultaneously to trigger a reset pulse generator 170 to reset thelow-speed decades 161 and 162. The switching of the bistable device 169closes a gate 171 and opens a second gate 172, diverting the next inputpulse from the forward" input 173 to the decade 160 to the "reverseinput 174. Owing to time delay's in the operation of gate 171 theswitching pulse will also step the reversible decade 160 by one pulse inthe forward direction. The reversible decade 160 now counts the inputpulses in reverse, while the low-speed decades 161 and 162 continue tocount normally in the forward direction.

The next multiple recognition state occurs when the low-speed decadesreach their unique recognition states and the high-speed decade 160reaches its reverse' recognition state y on Output 166. A recognitionpulse is delivered on the reverse recognition line 175, opening gate 176and preparing for the next input pulse to re-switch the bistable device169. The next input pulse thus switches the input back to the forwardinput 173 of the high-speed decade 160, at the same time Stepping thehigh-speed decade one pulse in the backward direction. Counting nowbegins in the forward direction until the forward recognition state withwhich the sequence began is again reached.

The recognition states for the low-speed decades 161 and 162 are set upin accordance with the required division ratio. The two recognitionstates x and y for the high-speed decade 160 are determined by therelation x-y=r-2, there r is the least significant digit of the divisionratio required.

What we claim is:

1. A digital counter stage including at least two switch- 4 ing deviceshaving at least two stable positions and having inputs arranged toreceive input pulses from a common input line through gating means whichdetermine the etlect of an input pulse on the respective switchingdevices and which are arranged to -be set each in correspondence withthe state of at least one of the switching devices in such a way that asuccession of input pulses causes the counter to progress through arepeated series of counting states, the counter including alsorecognition means for recognising when the counter has arrived at aselected one of its possible states and further gating means forresponding to this recognition and to Variable signals applied to saidgating means in dependence upon any selected counting state to which thecounter is to be reset in such a Way that the next consecutive inputpulse is employed as a resetting pulse for resetting the counter torecommence counting from said selected reset state.

2. A digital counter including a plurality of bistable devices eachhaving at least one input at which an applied pulse is effective tochange the device from one state to another, a common input line forpulses to be counted, and a plurality of gating devices each connectedbetween a said input of a bistable device and the common input line,each gating device having a further connection With at least onebistable device and receiving therefrom a signal dependent upon thecondition of the bistable device to determine the response of the gatingdevice to an input pulse, the association of the bistable devices andgating devices being such that a succession of input pulses causes thecounter to progress through a repeated series of counting states, thecounter including also a further plurality of gating devices eachconnected between a said input of a bistable device and a common resetline, recognition means responsive to the counter s reaching a selectedone of its possible states for delivering an output pulse and effectiveupon such recognition to direct the next successive input pulses fromthe common input line to the reset line and means for selectivelycontrolling in dependence upon any selected counting state to which thecounter is to be reset the response of the further gating devices to apulse appearing in the reset line whereby such a pulse sets the counterto said any selected one of its possible states.

3. A digital counter as claimed in claim 1, comprising a plurality ofstages arranged so that a stage generates an output pulse as it passesthrough a predetermined one iii of its possible states, the said outputpulse being applied as an input pulse to a succeeding stage of thecounter.

4. A digital counter as claimed in claim 3, arranged for the repetitivecounting of a preset interval, the switching devices of the counterforming two counter Sections each provided with recognition meansarranged when each section reaches a predetermined count to initiate theresetting of the said section and to transfer the input pulses `to theother section of the counter.

5. A counter as claimed in claim 3, including cascaded counter stagesinterconnected so that during a counting operation a higher ordercounter stage signifies to the next lower order counter stage that ithas reached the requisite count condition.

6. A counter as claimed in claim 5 including means by which thecondition of a higher order counter stage is signified to the next lowerorder counter stage by an output pulse which conditions a bistablecircuit connected between the two counter stages.

7. An electrical oscillation generator including a variable-frequencyoscillator, a fixed-frequency reference source, a variable-ratio dividerincluding a digital counter as claimed in claim l, arranged to count thecycles of the output Waveform of the Variable-frequency oscillator andto deliver an output pulse each time a selected number of cycles iscounted, and means for controlling the output frequency of the Variablefrequency oscillator so as to reduce to zero deviations of therepetition frequency of the pulses appearing at the divider output fromthat of the fixed-frequency reference source.

References Cited UNITED STATES PATENTS 2,970,761 2/1961 Berange' 235--923,064,'890 11/ 1962 Butler 235-92 3,l85,963 5/1965 Peterson et al.340-168 3,078,4l7 2/1963 Nick 328- 3,183,367 5/1965 Van Berkel 307-224JOHN S. HEYMAN, Primary Examiner.

J. F. MILLER, Assistant Exam'ner.

1. A DIGITAL COUNTER STAGE INCLUDING AT LEAST TWO SWITCHING DEVICESHAVING AT LEAST TWO STABLE POSITIONS AND HAVING INPUTS ARRANGED TORECEIVE INPUT PULSES FROM A COMMON INPUT LINE THROUGH GATING MEANS WHICHDETERMINE THE EFFECT OF AN INPUT PULSE ON THE RESPECTIVE SWITCHINGDEVICES AND WHICH ARE ARRANGED TO BE SET EACH IN CORRESPONDENCE WITH THESTATE OF AT LEAST ONE OF THE SWITCHING DEVICES IN SUCH A WAY THAT ASUCCESSION OF INPUT PULSES CAUSES THE COUNTER TO PROGRESS THROUGH AREPEATED SERIES OF COUNTING STATES, THE COUNTER INCLUDING ALSORECOGNITION MEANS FOR RECOGNISING WHEN THE COUNTER HAS ARRIVED AT ASELECTED ONE OF ITS POSSIBLE STATES AND FURTHER GATING MEANS FORRESPONDING TO THIS RECOGNITION AND TO VARIABLE SIGNALS APPLIED TO SAIDGATING MEANS IN DEPENDENCE UPON ANY SELECTED COUNTING STATE TO WHICH THECOUNTER IS TO BE RESET IN SUCH A WAY THAT THE NEXT CONSECUTIVE INPUTPULSE IS EMPLOYED AS A RESETTING PULSE FOR RESETTING THE COUNTER TORECOMMENCE COUNTING FROM SAID SELECTED RESET STATE.